1. Field of the Invention
The present invention relates to a programmable logic device having programmable switching means and a storage circuit used with the logic device.
2. Description of the Related Art
Integrated circuits in which logic gates can be programmed by a user have come into general use in recent years. Such integrated circuits are generally referred to as programmable logic devices (abbreviated to PLDs). A feature of the PLD is incorporation therein of a large number of active devices or passive devices which substantially operate a switches. Selective switching (on or off) of those switch devices permits a desired logical function to be implemented.
One of prior arts of the PLDs uses CMOS transmission gates, as disclosed in U.S. Pat. No. 4,695,740 issued to William S. Carter. As illustrated in FIG. 1, this prior art is comprised of four CMOS transmission gates 81 to 84, a flip-flop 85 for storing control data to selectively switch the CMOS transmission gates on and a buffer 86. Each of the CMOS transmission gate's comprises a P-channel MOS transistor and an N-channel MOS transistor whose drain-to-source paths are paralleled with each other and gates are each connected to selectively receive one of complementary outputs Q and Q of the flip-flop 85.
When, in this circuit, the flip-flop 85 is programmed previously such that Q=1 and Q=0, the transmission gates 81 and 82 are on, while the transmission gates 83 and 84 are off with the result that a signal is transferred from node A through buffer 86 to node B. Conversely, when Q=0 and Q=1, the transmission gates 83 and 84 are on, while the transmission gates 81 and 82 are off with the result that a signal is transferred from node B through buffer 86 to node A. In this way, the direction of transmission of a signal in this PLD is determined by data stored in the flip-flop.
The use of a CMOS transmission gate as a switching device as in the conventional PLD requires two transistors for a switching device. This will make circuit configuration complex and wiring for distributing control signals to the gates of transistors troublesome as compared with a switching device consisting of only one N-channel MOS transistor. Moreover, a two-transistor switching device will require an area on an integrated-circuit chip which is at least two times larger than that required for a switching device consisting of a single MOS transistor. This will result in poor integration density and thus a PLD with a large number of switch devices will require a very large chip area. As is well known, an increase in chip area decreases the number of chips per wafer and moreover reduces manufacturing yielding, thus leading to an increase in cost. In addition, an integrated circuit with a large chip area also requires a large package. This will decrease the number of integrated circuits to be mounted on a printed circuit board and further increase cost.
When the switch device is constructed from a single N-channel MOS transistor, on the other hand, a new problem differing from the above will arise. This arises from the well-known inherent characteristic of N-channel MOS transistors, i.e., the back gate bias effect. That is, to turn an N-channel MOS transistor on, its gate is set at a high supply voltage, for example, V.sub.DD. In this state, however, it is impossible to transmit a signal level in the neighborhood of V.sub.DD. As is well known, the N-channel MOS transistor cannot be turned on unless its gate potential is higher than its source potential by its threshold voltage (Vth). Thus, when the gate potential is V.sub.DD, the maximum potential that can be transmitted is as low as (V.sub.DD -Vth). Moreover, with the output potential in the neighborhood of (V.sub.DD -Vth), even if the N-channel MOS transistor is in the on state, its on resistance is noticeably high and thus high-speed operation cannot be expected. This will narrow the operating supply voltage range, decrease reliability and involve difficulties in implementing a programmable logic device.